1. Field of the Invention
The present invention relates to the fabrication of integrated circuit devices on semiconductor substrates, and more particularly to CMOS transistor fabrication methods for forming silicided metal gates.
2. Description of Related Art
Throughout the prior art, metal gate integration has proved difficult to achieve in a conventional process flow for CMOS transistors. Most metal gate materials are easily etched when exposed to the standard CMOS cleans for conventional processing, such as sulfuric peroxide (SP) cleans, hydrogen fluoride (HF) etches, and the like. Initial attempts to mitigate this etching concern has centered on capping the metal gate layer with polysilicon. This method, however, is highly subject to interface effects and introduces typical polysilicon resistance related issues. In conventional gate electrodes using polysilicon/silicide, such as Poly-Si/WSix, the increased resistance causes a large gate RC delay, thereby degrading performance. Generally, resistance is reduced by preventing detrimental transition-metal reactions during processing, particularly with oxygen.
The protection of the metal gate during conventional processing against transistor performance degradation, such as Tinv-equivalent thickness of gate capacitance, Ion source to drain current when device is on, and R-resistance of gate stack, is especially important when the metal is prone to degradation through unwanted etching and cross-contamination. Significantly, a process that protects the metal gate while allowing for the source and drain silicide to be of a different silicide than the gate silicide yields performance dividends and reduces complexity. Voltage threshold tailoring through metal gate implementation is also desirable, and may be achievable if a metal gate protection scheme can be implemented at the onset.
The current prior art has not sufficiently accounted for unwanted etching of the metal gate surface during cleans or cross-contamination during processing. In addition, predetermined voltage tailoring using various metal gates and metal suicides remain desirable goals during CMOS processing.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a CMOS fabrication process for metal gate protection.
It is another object of the present invention to provide a method for sealing a metal gate by spacer and capping silicide, which allows for cleans and minimizes cross contamination.
A further object of the invention is to provide a method for metal gate protection that allows the source/drain silicide to be different than the gate silicide.
It is yet another object of the present invention to provide a method for metal gate protection that enables a wet etch for gate metal and minimizes gate dielectric attack or damage.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.